This invention relates to an oxide film isolation process.
In the manufacture of semiconductor integrated circuit devices, it has become an important process to provide an isolation layer in order to make respective elements electrically independent. One of the techniques for forming the isolation layer is the oxide film isolation process (refer to `Denshi Zairyo (Electronic Material)` March 1974, pp. 53 - 54). This process forms the isolation layer in such way that a groove is formed by, for example, chemical etching in that area of a semiconductor substrate in which the isolation layer is to be formed, and that the vicinity of the groove portion is subjected to selective oxidation. The merits of the oxide film isolation process are as follows. (1) Since the surface of the semiconductor substrate surface can be made flat, an internal wiring which is disposed on the semiconductor substrate surface is prevented from being disconnected. (2) Since the isolation and the patterning of base and collector contacts can be concurrently performed by the use of a single mask, the alignment error of the mask need not be considered, whereby the semiconductor chip area can be diminished. (3) Even when, in the step of selective oxidation, the mask pattern is formed with defective parts in an area other than the area for the selective oxidation on account of, e.g., pinholes in a photoresist film, the defective parts merely have the oxide film grown thereat and they exert no great influence on the essential circuit characteristics, so that a sharp enhancement of yield can be expected. With this process, however, unless the bottom part of the isolation layer reaches a buried layer, inferior isolation (that is, the short-circuit between the semiconductor substrate and a base layer) will take place. The bottom part of the isolation layer must therefore be designed so as to be deep enough to arrive at the buried layer. The lateral width of the isolation layer is accordingly made large, so that the area which the isolation layer occupies in the semiconductor chip surface becomes large.